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Tuesday, 16 December 2014 00:00

Integration of STT-MRAM model into CACTI simulator

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Arcaro, S.; Di Carlo, S.; Indaco, M.; Pala, D.; Prinetto, P.; Vatajelu, E.I., in Design & Test Symposium (IDT), 2014 9th International , vol., no., pp.67,72, 16-18 Dec. 2014



In the last decade, academies and private companies have actively explored emerging memory technologies. STT-MRAM in particular is experiencing a rapid development but it is facing several challenges in terms of performance and reliability. Several techniques at cell level have been proposed to mitigate such issues but currently few tools and methodologies exist to support designers in evaluating the impact that specific micro-level design choices can determine on the STT-MRAM macro design. In this paper we present a system-level tool based on CACTI simulator to assist memory system designers. We use our tool to generate high-performance and low-power cache memories comparing performance, energy consumption, and area with traditional SRAM.


  •  BIBTEX:
author={Arcaro, S. and Di Carlo, S. and Indaco, M. and Pala, D. and Prinetto, P. and Vatajelu, E.I.},
booktitle={Design Test Symposium (IDT), 2014 9th International},
title={Integration of STT-MRAM model into CACTI simulator},
  • DOI: 10.1109/IDT.2014.7038589
  • KEYWORDS: MRAM devices, cache storage, integrated circuit design, integrated circuit reliability, low-power electronics


Read 1921 times Last modified on Wednesday, 10 June 2015 16:33

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