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Thursday, 24 March 2016 19:14

Cache- and Register-aware System Reliability Evaluation based on Data Lifetime Analysis

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Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, IEEE VLSI Test Symposium 2016 (VTS'16)

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Abstract

Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact product time-to-market. This paper introduces a new approach to evaluate, at early design phase, the reliability of a computing system running a software. The approach can be used when the hardware architecture is not completely defined yet. In order to be independent of the hardware architecture and at the same time accurate, we propose to use the Low-Level Virtual Machine (LLVM) framework. In addition, to reduce the reliability evaluation time, our approach consists in analyzing the variable lifetimes to compute the probability of masked faults. Finally, to achieve a better characterization we propose to consider also the presence of caches and register files. For this purpose, a cache emulator as well as a register file emulator are developed. Simulations run with our approach produce very similar results to those run with a hardware-based fault injector. This proves the accuracy of our approach to evaluate system reliability with a gain in the simulation time and without requiring a hardware platform..

Details

  •  BIBTEX:
@INPROCEEDINGS{7477299, 
author={M. Kooli and F. Kaddachi and G. Di Natale and A. Bosio}, 
booktitle={2016 IEEE 34th VLSI Test Symposium (VTS)}, 
title={Cache- and register-aware system reliability evaluation based on data lifetime analysis}, 
year={2016}, 
pages={1-6}, 
keywords={cache storage;fault diagnosis;flip-flops;reliability;time to market;virtual machines;LLVM framework;cache emulator;computing system;data lifetime analysis;hardware architecture;hardware-based fault injector;low-level virtual machine framework;masked faults probability;product time-to-market;register file emulator;register files;software reliability;system reliability;variable lifetimes;Clocks;Computer architecture;Hardware;Random access memory;Registers;Reliability;Software;Data Cache;Hardware Faults;LLVM;Lifetime;RAM;Reliability}, 
doi={10.1109/VTS.2016.7477299}, 
month={April},}
  • DOI: 10.1109/VTS.2016.7477299
  • KEYWORDS: cache storage;fault diagnosis;flip-flops;reliability;time to market;virtual machines;LLVM framework;cache emulator;computing system;data lifetime analysis;hardware architecture;hardware-based fault injector;low-level virtual machine framework;masked faults probability;product time-to-market;register file emulator;register files;software reliability;system reliability;variable lifetimes;Clocks;Computer architecture;Hardware;Random access memory;Registers;Reliability;Software;Data Cache;Hardware Faults;LLVM;Lifetime;RAM;Reliability

 

Read 1981 times Last modified on Tuesday, 17 January 2017 19:14

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