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Thursday, 24 March 2016 19:16

Microprocessor Reliability-Performance Tradeoffs Assessment at the Microarchitecture Level

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S.Tselonis, M.Kaliorakis, N.Foutris, G.Papadimitriou, D.Gizopoulos, IEEE VLSI Test Symposium (VTS 2016), Las Vegas, NV, USA, April, 2016

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Abstract

Early decisions in microprocessor design require a careful consideration of the corresponding performance and reliability implications of transient faults. The size and organization of important on-chip hardware components such as caches, register files and buffers have a direct impact on both the microprocessor resilience to soft errors and the execution time of the applications. In this paper, we employ a state-of-the-art x86-64 full-system micro-architectural simulator and a comprehensive fault injection framework built on top of it to deliver a detailed evaluation of the reliability and performance tradeoffs for major hardware components across several important parameters of their design (size, associativity, write policy, etc.). We also propose a simple and flexible fitness function that measures the aggregate effect of such design changes on the reliability and the performance of the studied workload.

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  •  BIBTEX:
@INPROCEEDINGS{7477300, 
author={S. Tselonis and M. Kaliorakis and N. Foutris and G. Papadimitriou and D. Gizopoulos}, 
booktitle={2016 IEEE 34th VLSI Test Symposium (VTS)}, 
title={Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level}, 
year={2016}, 
pages={1-6}, 
keywords={fault diagnosis;integrated circuit design;integrated circuit reliability;microprocessor chips;radiation hardening (electronics);transient analysis;buffers;caches;fault injection;microarchitecture level;microprocessor design;microprocessor reliability;microprocessor resilience;on-chip hardware components;register files;soft errors;transient faults;x86-64 full system microarchitectural simulator;Benchmark testing;Hardware;Microarchitecture;Microprocessors;Registers;Reliability engineering;fault injection;microprocessors;performance;reliability estimation;transient faults}, 
doi={10.1109/VTS.2016.7477300}, 
month={April},}
  • DOI: 10.1109/VTS.2016.7477300
  • KEYWORDS: fault diagnosis;integrated circuit design;integrated circuit reliability;microprocessor chips;radiation hardening (electronics);transient analysis;buffers;caches;fault injection;microarchitecture level;microprocessor design;microprocessor reliability;microprocessor resilience;on-chip hardware components;register files;soft errors;transient faults;x86-64 full system microarchitectural simulator;Benchmark testing;Hardware;Microarchitecture;Microprocessors;Registers;Reliability engineering;fault injection;microprocessors;performance;reliability estimation;transient faults

 

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