Clereco

Cross-Layer Early Reliability Evaluation for the Computing cOntinuum

Abstract

One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper, we estimate the STT-MRAM cell reliability under fabrication- and aging-induced process variability, by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and, as a result, we propose a power- and aging-aware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation), but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability, and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis, the appropriate value of this control voltage is determined.

Details

•  BIBTEX:

@INPROCEEDINGS{7138748, 
  author={E. I. Vatajelu and R. Rodriguez-Montañés and S. Di Carlo and M. Indaco and M. Renovell and P. Prinetto and J. Figueras}, 
  booktitle={Test Symposium (ETS), 2015 20th IEEE European}, 
  title={Power-aware voltage tuning for STT-MRAM reliability}, 
  year={2015}, 
  pages={1-6}, 
  keywords={integrated circuit reliability;power aware computing;random-access storage;STT-MRAM reliability;aging-induced process variability;cell failure probability;circuit level variability mitigation technique;control voltage tuning;fabrication-induced process variability;power consumption;power-aware voltage tuning;spin-transfer-torque magnetic random access memory;Magnetic hysteresis;Magnetic tunneling;Reliability;Resistance;Stress;Threshold voltage;Voltage control;Endurance;Power-Aware Analysis;Process Variability;Reliability;STT-MRAM;Voltage Tuning}, 
  doi={10.1109/ETS.2015.7138748}, 
  month={May},}

• DOI: 10.1109/ETS.2015.7138748
• KEYWORDS: integrated circuit reliability;power aware computing;random-access storage;STT-MRAM reliability;aging-induced process variability;cell failure probability;circuit level variability mitigation technique;control voltage tuning;fabrication-induced process variability;power consumption;power-aware voltage tuning;spin-transfer-torque magnetic random access memory;Magnetic hysteresis;Magnetic tunneling;Reliability;Resistance;Stress;Threshold voltage;Voltage control;Endurance;Power-Aware Analysis;Process Variability;Reliability;STT-MRAM;Voltage Tuning