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Monday, 11 May 2015 00:00

STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations

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E. I. Vatajelu, R. Rodriguez-Montañes, M. Indaco, P. Prinetto and J. Figueras, Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, Naples, 2015, pp. 1-6.

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Abstract

The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. For this reason, alternate solutions are being proposed in literature, to possibly replace charge based memories. One of the most promising of these solutions is the spin-transfer-torque magnetic random access memory (STT-MRAM). To evaluate the viability of such solution, one must understand how it behaves under the effect of the various reliability degradation factors. In this paper we propose a methodology which allows for fast reliability evaluation of an STT-MRAM cell under process, voltage, and temperature variations. Our proposed method allows for a sensitivity analysis which will show the designer/test engineer which is the main reliability concern of a certain design. The method is general, and it can be applied to any memory design.

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  •  BIBTEX:
@INPROCEEDINGS{7127377, 
  author={E. I. Vatajelu and R. Rodriguez-Montañes and M. Indaco and P. Prinetto and J. Figueras}, 
  booktitle={Design Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on}, 
  title={STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations}, 
  year={2015}, 
  pages={1-6}, 
  keywords={CMOS memory circuits;MRAM devices;integrated circuit reliability;CMOS based memories;STT-MRAM cell reliability evaluation;process variation;reliability degradation factors;sensitivity analysis;spin-transfer-torque magnetic random access memory;temperature variation;voltage variation;Degradation;Magnetic tunneling;Magnetization;Resistance;Temperature distribution;Thermal stability;Process Variation;Reliability;STT-MRAM cell;Temperature;Voltage Variation;statistical analysis}, 
  doi={10.1109/DTIS.2015.7127377}, 
  month={April},}
  • DOI: 10.1109/DTIS.2015.7127377
  • KEYWORDS: CMOS memory circuits;MRAM devices;integrated circuit reliability;CMOS based memories;STT-MRAM cell reliability evaluation;process variation;reliability degradation factors;sensitivity analysis;spin-transfer-torque magnetic random access memory;temperature variation;voltage variation;Degradation;Magnetic tunneling;Magnetization;Resistance;Temperature distribution;Thermal stability;Process Variation;Reliability;STT-MRAM cell;Temperature;Voltage Variation;statistical analysis

 

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