NOTE! This site uses cookies and similar technologies.

If you not change browser settings, you agree to it. Learn more

I understand
Monday, 26 May 2014 00:00

A novel adaptive fault tolerant flip-flop architecture based on TMR

Rate this item
(0 votes)

Cassano, L.; Bosio, A.; Di Natale, G., in Test Symposium (ETS), 2014 19th IEEE European , vol., no., pp.1,2, 26-30 May 2014

PDFDOI

Abstract

The use of Triple Modular Redundancy (TMR) was historically introduced long time ago for improving reliability of computer systems [1]. Recently, the advances in miniaturizing of CMOS devices made digital circuits more and more unreliable. The current trend goes towards the Internet of Things and the cloud computing, where small devices have high requirements in terms of reduced power consumption and increased reliability [2]. Classical TMR solutions allow for high reliability but they cannot satisfy low-power requirements, since they consume about three times more than the equivalent single device. However, the type of applications that are implemented in the new cloud scenario do not require high reliability all the time, but it can be assumed that some computations are more important, and thus require to be executed by a reliable hardware, while other computations are less important, and thus they can tolerate failures [3].

Details

  •  BIBTEX:
@INPROCEEDINGS{6847831,
author={Cassano, L. and Bosio, A. and Di Natale, G.},
booktitle={Test Symposium (ETS), 2014 19th IEEE European},
title={A novel adaptive fault tolerant flip-flop architecture based on TMR},
year={2014},
month={May},
pages={1-2},
doi={10.1109/ETS.2014.6847831},
}
  • DOI: 10.1109/ETS.2014.6847831
  • KEYWORDS: design for testability, fault tolerance, flip-flops, integrated circuit reliability, logic design

 

Read 1668 times Last modified on Friday, 12 June 2015 14:43

Add comment


Security code
Refresh