May 28-29, 2015
Cluj-Napoca, Romania

 
 

Advanced multifunctional computing systems realized in forthcoming technologies hold the promise of a significant increase of the computational capability that will offer end-users ever improving services and functionalities (e.g., next generation mobile devices, cloud services, etc.). However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable posing a threat to our society that is depending on the computers and electronic devices in every aspect of human activities. As an example, the 2012 ITRS roadmap lists aging in semiconductor devices as one of the few most difficult challenges concerning reliability.


This workshop provides a unique chance to join experts from three on-going European projects that address several reliability challenges.The topics that will be covered include fault modeling in forthcoming technologies, careful early reliability evaluation of complex designs as well as techniques to address No Failure Found (NFF), which is caused by a combination of test escapes, aging, and environmental impact.

 

GENERAL CHAIRS

Stefano DI CARLO, Pol. di Torino IT

Matteo SONZA REORDA, Pol. di Torino IT


PROGRAM CHAIRS

Artur JUTMAN, Testonica Lab

Dimitris GIZOPOULOS, Univ. Of Athens, GR


ORGANIZATION

Giorgio DI NATALE, LIRMM, FR


PROGRAM COMMITTEE

  1. • A. Jutman, Testonica

  2. • C. Lotz, Aster

  3. • C. Laudert, Infineon

  4. • H. Kerkhoff, U. Twente

  5. • E. Larsson, U. Lund

  6. • J. Raik, U. Tallin

  7. • M. Sonza Reorda, Pol. Torino

  8. • R. Krenz-Baath, Hamm-Lippstadt U.

  9. • S. Di Carlo, Pol. Torino

  10. • G. Di Natale, LIRMM/CNRS

  11. • D. Gizopoulos, U. Athens

  12. • A. Gonzalez, UPC

  13. • R. Canal, UPC

  14. • A. Grasset, Thales

  15. • T. Seceleanu, ABB

  16. • R. Mariani, Yogitech

  17. • M. Azimane, NXP


The Workshop is organized by


Board and SoC Test Instrumentation for Ageing and No Failure Found (https://fp7-bastion.eu)



Cross Layer Early Reliability Evaluation for the Computing cOntinuum (https://www.clereco.eu)


European library-based flow of embedded silicon test instruments (https://www.elesis.eu)



REGISTRATION AND LOCATION


The workshop is co-located with the IEEE European Test Symposium 2015. Please visit ETS’15 website for registration and accommodation info. (https://www.ets15.ro).

 

Scope

Program

May 28th, 2015

16:00 – 16:10 Welcome (S. Di Carlo, M. Sonza Reorda POLITO)


16:10 - 17:00 Keynote1 Prof. Adit Singh (Auburn U.) Targeting Test Escapes to Improve Reliability: What Defects Should We Be Focusing On?

Session chair: M. Sonza Reorda (POLITO)

Abstract: We make the case based on recent production data that partial and fully open defects appear to be the biggest source of test escapes in state-of-the-art IC manufacturing. However, these two types of defects require very different test methodologies. Partial opens, such as via voids, are often undetectable by electrical testing and require some form of stress tests such as burn-in for screening. Full open defects in CMOS, on the other hand, can be detected by conventional tests, but are often missed by the stuck-at and TDF tests commonly used in production testing. We discuss the best available strategies to target these manufacturing defects that are a key contributor to IC unreliability.


Bio: Adit  Singh received his B. Tech. from IIT Kanpur and the M.S. and Ph.D. from Virginia Tech, all in Electrical Engineering. He is currently James B. Davis Professor of Electrical and Computer Engineering at Auburn University in the USA. His research interests span all aspects of VLSI technology; he is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has published over two hundred research papers, and holds international patents that have been licensed to industry.  Dr. Singh was elected a Fellow of IEEE in 2002 for “contributions to defect based testing and test optimization in VLSI circuits”. He is a past Chair of the IEEE Test Technology Technical Council.


17:00 - 17:20 Coffee Break


17:20 -18:50 Session 1 Aging and reliability threats in next generation technologies.

Session chair: G. Di Natale (LIRMM)


  1. • Hans Kerkhoff (U. Twente): Ageing mechanisms: effect detection and test instrumentation

  2. • Maksim Jenihhin (Tallinn University of Technology): Identification and Rejuvenation of NBTI-Critical Paths

  3. • Christophe Lotz (Aster): No Fault Found – Between dream and reality

  4. • Marc Riera (UPC) Soft-Error Vulnerability Evolution: A 4D study (bulk/SOI, planar/FinFET)



19:00 - 20:30 Wine and Cheese Panel: "Which are the most critical challenges in terms of reliability today?"

Moderator: A. Jutman (Testonica Lab)



May 29th, 2015

09:00 - 10:00 Keynote2 M. Azimane (NXP)

ELESIS: Challenges of Testing in Europe

Session chair: H. Kerkhoff (U. Twente) 

Short bio

Dr. Azimane is the Coordinator of the European Consortium ELESIS, and the project manager of Design for Test within NXP Semiconductors, Eindhoven, The Netherlands.

He received the Master Degree in Physics Electronics with Honors from the University of Abd El Malek Essaâdi, Morocco, and PhD Degree with Cum-Laude from the University of Granada, Spain. Joined Philips Research in 1999, where he developed innovative solutions on defect-oriented test for digital circuits, embedded memories for Mobile phones, Automotive and RF-Identification systems. He has built strong expertise on developing low cost test solutions for Mixed/Analog Signal Circuits while improving products quality to meet high quality requirements for automotive applications.


Short abstract of the presentation

Semiconductor companies in Europe will bring in the coming years many innovative applications to the market, in a form of variety of application domains: Road safety, personal healthcare, secured wireless communications, avionics, smart-lighting and advanced consumer electronics. To stay competitive world-wide, European semiconductors has to offer the best quality, the fastest time to market within affordable test cost.

This presentation will give an overview about the main results and achievement that we achieved so far in ELESIS.


10:00 - 10:30 Coffee break


10:30 -12:00 Session 2 Early reliability estimation role in next generation system’s designs.

Session chair: S. Di Carlo (POLITO)


  1. • G. Di Natale (LIRMM):  Software-Level Reliability Evaluation for Hardware Faults

  2. • A. Vallero (Politecnico di Torino):  Bayesian inference of software resiliency

  3. • F. Sforza (Yogitech): reliability in automotive applications


12:00 - 13:00 Lunch


13:00 -14:30 Session 3 On-Line testing

Session chair: J. Raik (U. Tallinn)

  1. • Artur Jutman  (Testonica Lab): IEEE 1687 monitoring infrastructure for ageing failure management

  2. • Ahmed Sokar (Infineon): Measurement instruments for analog parameters

  3. • Matteo Sonza Reorda (Politecnico di Torino): in-field test and monitoring

  4. • Tiberiu Seceleanu (ABB): Extra-functional properties in industrial systems-How to consider them in (early) design stages

14:30 - 14:45 Closing