Clereco
Cross-Layer Early Reliability Evaluation for the Computing cOntinuum
Cross-Layer Early Reliability Evaluation for the Computing cOntinuum
CLERECO is active in the organization of International Workshops bringing togeter worldwide experts in different aspects of reliability problems
With the proliferation of integrated circuits implemented in the most advanced process technologies, there is a growing need to jointly analyze the effect of multiple sources of failures including variability and aging and to understand, early in the design cycle, their impact on system reliability.
Today, conservative margins are required to ensure devices operate correctly over their full lifetime, despite the impact of aging effects (BTI, HCI) and failure mechanisms such as EM. New methodologies for improved cross-layer modeling and mitigation, if planned early in the design of a product, have the potential to remove unnecessary conservatism, reduce power and cost and improve yield.
This workshop is focused on sharing new research on techniques and methodologies for modeling the effects of failures due to transistor aging, variability and other mechanisms all the way from the cell level to system level. New approaches to perform early estimations of system reliability are much needed to enable cost-effective designs jointly optimized with respect to reliability, power consumption as well as costs.
Research in the last few years has focused on approximate computing as a means to overcome the energy scaling barrier of computer systems. Such savings can be achieved by utilizing the inherent error resilience of algorithms in many application domains such as signal processing, multimedia, data analytics and computational engineering, among others. Indeed, fully accurate arithmetic in specific phases of a computation in those applications may have only a marginal effect on output quality, especially if combined with error correction frameworks such as iterative refinement. Thus, accurate execution may be traded off with lower energy consumption by providing the ability to scale supply voltage below nominal values or to use lower precision arithmetic (i.e. 8 or 16 bit), thus, trading off low energy with quality of output results.
Rather than focusing on a single layer, designing such systems in a general-purpose computing environment requires a holistic view of all layers from algorithms, programming models, system software, and hardware down to the transistor level. This half-day workshop is an inter-disciplinary effort to bring together researchers from the areas of mathematics, computer science, computer and electrical engineering to discuss challenges, risks and opportunities of approximate computing in all design layers. Papers will not be published in proceedings, so submitting to WAPCO will not preclude future publication opportunities. We are soliciting original papers on topics that include but are not limited to the following:
Advanced multifunctional computing systems realized in forthcoming technologies hold the promise of a significant increase of the computational capability that will offer end-users ever improving services and functionalities (e.g., next generation mobile devices, cloud services, etc.). However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable posing a threat to our society that is depending on the computers and electronic devices in every aspect of human activities. As an example, the 2012 ITRS roadmap lists aging in semiconductor devices as one of the few most difficult challenges concerning reliability.
This workshop provides a unique chance to join experts from three on-going European projects that address several reliability challenges.The topics that will be covered include fault modeling in forthcoming technologies, careful early reliability evaluation of complex designs as well as techniques to address No Failure Found (NFF), which is caused by a combination of test escapes, aging, and environmental impact
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