Partner Polito presents the paper SIFI a reliability evaluation framework for soft-errors built on top of Multi2Sim at 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS’17)

Partner UoA presents the paper RT Level vs. Microarchitecture Level Reliability Assessment: Case Study on ARM Cortex-A9 CPU at the 47th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2017)

Partner UoA presents the paper MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment at the the 44th Annual International Symposium on Computer Architecture (ISCA '17)

Partner Polito presents the poster Microarchitecture Level Reliability Comparison of Modern GPU Designs: First Findings at the 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'17)

Partner UoA presents the paper Performance-Aware Reliability Assessment of Heterogeneous Chips at 35th IEEE VLSI Test Symposium 2017 (VTS17)

Torino, December, 2016. The research program of the joint FP7 Collaboration Project CLERECO (Grant No. 611404) aiming to investigate new design methods for early reliability evaluation of digital systems in the forthcoming computing continuum is now successfully concluded.

Partners POLITO, UPC, UoA and CRNS are going to present innovative results and tools of the CLERECO project at the XXXI edition of the Design of Circuits and Integrated Systems Conference, DCIS 2016, held in Granada, Spain from 23rd to 25th November 2016.

Partner POLITO presents the paper Cross-Layer System Reliability Assessment Against Hardware Faults at International Test Conference, ITC 2016 in Fort Worth Texas, TX.

Partner POLITO presented the project at the special session organized during the PATMOS 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation 2016, Bremen, Germani 21-23 September 2016.