The first paper presents a methodology for predicting the reliability of an STT-MRAM based memory (assuming high thermal stability). The reliability estimation is performed at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve desired reliability target for the memory under study.
The second paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated in- frastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.
If you are attending the conference, don't miss the presentations.