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Tuesday, 18 July 2017 06:35

Performance-aware reliability assessment of heterogeneous chips

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A. Chatzidimitriou, M. Kaliorakis, S. Tselonis and D. Gizopoulos, 2017 IEEE 35th VLSI Test Symposium (VTS), Las Vegas, NV, 2017, pp. 1-6. doi: 10.1109/VTS.2017.7928940



Abstract: Technology evolution has raised serious reliability considerations, as transistor dimensions shrink and modern microprocessors become denser and more vulnerable to faults. Reliability studies have proposed a plethora of methodologies for assessing system vulnerability which, however, highly rely on traditional reliability metrics that solely express failure rate over time. Although Failures In Time (FIT) is a very strong and representative reliability metric, it may fail to offer an objective comparison of highly diverse systems, such as CPUs against GPUs or other accelerators that are often employed to execute the same algorithms implemented for these platforms..


author={A. Chatzidimitriou and M. Kaliorakis and S. Tselonis and D. Gizopoulos}, 
booktitle={2017 IEEE 35th VLSI Test Symposium (VTS)}, 
title={Performance-aware reliability assessment of heterogeneous chips}, 
  • 10.1109/VTS.2017.7928940
  • KEYWORDS: failure analysis;graphics processing units;CPU;FIT;GPU;accelerators;failure rate;failures in time;heterogeneous systems;modern microprocessors;parallel code;performance-aware evaluation methodology;register file;reliability evaluation methodology;reliability metrics;serial code;statistical fault injection;system vulnerability;technology evolution;transistor dimensions;workload execution failure;Benchmark testing;Computer architecture;Graphics processing units;Integrated circuit reliability;Measurement;Microarchitecture;CPU;GPU;fault injection;microarchitectural;performance;reliability;simulators;vulnerability evaluation
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