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Thursday, 24 March 2016 19:17

Faults in Data Prefetchers: Performance Degradation and Variability

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N.Foutris, A.Chatzidimitriou, D.Gizopoulos, J.Kalamatianos, V.Sridharan, IEEE VLSI Test Symposium (VTS 2016), Las Vegas, NV, USA, April, 2016.

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Abstract

High-performance microprocessors employ data prefetchers to mitigate the ever-growing gap between CPU computing rates and memory latency. Technology scaling along with low voltage operation exacerbates the likelihood and rate of hard (permanent) faults in technologies used by prefetchers such as SRAM and flip flop arrays. Faulty prefetch behavior does not affect correctness but can be detrimental to performance. Hard faults in data prefetchers (unlike their soft counterparts which are rare) can cause significant single-thread performance degradation and lead to large performance variability across otherwise identical cores. In this paper, we characterize in-depth both of these aspects in microprocessors suffering from multiple hard faults in their data prefetcher components. Our study reveals fault scenarios in the prefetcher table that can degrade IPC by more than 17%, while faults in the prefetch input and request queues can slow IPC up to 24% and 26%, respectively, compared to fault-free operation. Moreover, we find that a faulty data prefetcher can substantially increase the performance variability across identical cores: the standard deviation of IPC loss for different benchmarks can be more than 4.5%.

Details

  •  BIBTEX:
@INPROCEEDINGS{7477312, 
author={N. Foutris and A. Chatzidimitriou and D. Gizopoulos and J. Kalamatianos and V. Sridharan}, 
booktitle={2016 IEEE 34th VLSI Test Symposium (VTS)}, 
title={Faults in data prefetchers: Performance degradation and variability}, 
year={2016}, 
pages={1-6}, 
keywords={microprocessor chips;storage management;CPU computing rates;IPC loss;SRAM;data prefetcher components;faulty prefetch behavior;flip flop arrays;high-performance microprocessors;low voltage operation;memory latency;multiple hard faults;performance variability;single-thread performance degradation;technology scaling;Arrays;Benchmark testing;Circuit faults;Prefetching;Random access memory;Standards;Training;dependable performance;microarchitectural simulators;performance degradation;performance variability;permanent faults}, 
doi={10.1109/VTS.2016.7477312}, 
month={April},}
  • DOI: 10.1109/VTS.2016.7477312
  • KEYWORDS: microprocessor chips;storage management;CPU computing rates;IPC loss;SRAM;data prefetcher components;faulty prefetch behavior;flip flop arrays;high-performance microprocessors;low voltage operation;memory latency;multiple hard faults;performance variability;single-thread performance degradation;technology scaling;Arrays;Benchmark testing;Circuit faults;Prefetching;Random access memory;Standards;Training;dependable performance;microarchitectural simulators;performance degradation;performance variability;permanent faults

 

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