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Thursday, 24 March 2016 19:19

System-level Reliability Evaluation through Cache-aware Software-based Fault Injection

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Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, IEEE DDECS 2016, April 20-22, 2016, Košice, Slovakia

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Abstract

Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact the product time-to-market. In this paper, we propose a novel fault injection technique to evaluate the reliability of a computing system running a software at early design stage where the hardware architecture is not completely defined yet. The proposed approach efficiently operates on the original source code of the software in order to inject transient faults in the data or the instructions. To be accurate and to achieve a better characterization of the system, we simulate faults occurring in the system memory units such as the data cache and the RAM by developing a system emulator. To validate our approach, we compare the simulation results to those obtained with an FPGA-based fault injector. The similarity of the results proves the accuracy of our approach to evaluate system reliability with a gain in the execution time and without requiring a fully defined hardware system.

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  •  BIBTEX:
@INPROCEEDINGS{7482446, 
author={F. Kaddachi and M. Kooli and G. Di Natale and A. Bosio and M. Ebrahimi and M. Tahoori}, 
booktitle={2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS)}, 
title={System-level reliability evaluation through cache-aware software-based fault injection}, 
year={2016}, 
pages={1-6}, 
keywords={cache storage;field programmable gate arrays;random-access storage;software reliability;FPGA-based fault injector;RAM;cache-aware software-based fault injection;computing system;data cache;design costs;fault injection technique;fully defined hardware system;product time-to-market;software reliability;system-level reliability evaluation;transient faults;Computer architecture;Hardware;Random access memory;Reliability engineering;Software;Software reliability;Cache;Fault Injection;Memory;RAM;Reliability;Soft Errors;Software}, 
doi={10.1109/DDECS.2016.7482446}, 
month={April},}
  • DOI: 10.1109/DDECS.2016.7482446
  • KEYWORDS: cache storage;field programmable gate arrays;random-access storage;software reliability;FPGA-based fault injector;RAM;cache-aware software-based fault injection;computing system;data cache;design costs;fault injection technique;fully defined hardware system;product time-to-market;software reliability;system-level reliability evaluation;transient faults;Computer architecture;Hardware;Random access memory;Reliability engineering;Software;Software reliability;Cache;Fault Injection;Memory;RAM;Reliability;Soft Errors;Software

 

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