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Wednesday, 03 May 2017 13:47

RIIF-2: Toward the next generation reliability information interchange format

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A. Savino, S. Di Carlo, A. Vallero, G. Politano, D. Gizopoulos, A. Evans, IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), 4-6 July 2016

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Abstract

Abstract: This paper describes the joint effort of the two FP7 EU projects CLERECO and MoRV toward the definition of an extended reliability information exchange format able to manage reliability information for the full system stack, from technology up to the software level. The paper starts from the RIIF language initiative, proposing a set of new features to improve the expression power of the language and to extend it to the software layer of a system. The proposed extended reliability information exchange format named RIIF-2 has the potential to support the development of next generation reliability analysis tools that will help to fully include reliability evaluation into an automated design flow, pushing cross-layer reliability considerations at the same level of importance as area, timing and power consumption when performing design exploration for new products.

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  • BIBTEX:
@INPROCEEDINGS{7604693, 
author={A. Savino and S. Di Carlo and A. Vallero and G. Politano and D. Gizopoulos and A. Evans}, 
booktitle={2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)}, 
title={RIIF-2: Toward the next generation reliability information interchange format}, 
year={2016}, 
pages={173-178}, 
keywords={integrated circuit design;integrated circuit reliability;CLERECO;FP7 EU projects;MoRV;RIIF language initiative;RIIF-2;automated design flow;cross-layer reliability considerations;expression power;extended reliability information exchange format;full system stack;next generation reliability analysis tools;reliability evaluation;software layer;Hardware;Integrated circuit reliability;Random access memory;Reliability engineering;Software;Software reliability;design flow;modeling languages;reliability;robustness}, 
doi={10.1109/IOLTS.2016.7604693}, 
month={July},}
  • DOI: 10.1109/IOLTS.2016.7604693
  • KEYWORDS: integrated circuit design;integrated circuit reliability;CLERECO;FP7 EU projects;MoRV;RIIF language initiative;RIIF-2;automated design flow;cross-layer reliability considerations;expression power;extended reliability information exchange format;full system stack;next generation reliability analysis tools;reliability evaluation;software layer;Hardware;Integrated circuit reliability;Random access memory;Reliability engineering;Software;Software reliability;design flow;modeling languages;reliability;robustness
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