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Wednesday, 03 May 2017 13:55

Cross-layer system reliability assessment framework for hardware faults

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A. Vallero, A. Savino, G. Politano, S. Di Carlo, A. Chatzidimitriou, S. Tselonis, M. Kaliorakis, D. Gizopoulos, M. Riera, R. Canal, A. Gonzalez, M. Kooli, A. Bosio, G. Di Natale, 2016 IEEE International Test Conference (ITC), Fort Worth, TX, 2016, pp. 1-10., doi: 10.1109/TEST.2016.7805863

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Abstract

Abstract: System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.

Details

  • BIBTEX:
@INPROCEEDINGS{7805863, 
author={A. Vallero and A. Savino and G. Politano and S. Di Carlo and A. Chatzidimitriou and S. Tselonis and M. Kaliorakis and D. Gizopoulos and M. Riera and R. Canal and A. Gonzalez and M. Kooli and A. Bosio and G. Di Natale}, 
booktitle={2016 IEEE International Test Conference (ITC)}, 
title={Cross-layer system reliability assessment framework for hardware faults}, 
year={2016}, 
pages={1-10}, 
keywords={Bayes methods;circuit reliability;FIT rates;component-based Bayesian model;computing systems reliability;cross-layer system reliability assessment framework;early design phases;estimation model;hardware components;hardware faults;masking probabilities;microarchitecture level;protection mechanisms;reliability reports;software components;Bayes methods;Computational modeling;Estimation;Hardware;Software;Software reliability;cross-layer reliability;dependable computing system;reliability modeling}, 
doi={10.1109/TEST.2016.7805863}, 
month={Nov},}
  • DOI: 10.1109/TEST.2016.7805863
  • KEYWORDS: Bayes methods;circuit reliability;FIT rates;component-based Bayesian model;computing systems reliability;cross-layer system reliability assessment framework;early design phases;estimation model;hardware components;hardware faults;masking probabilities;microarchitecture level;protection mechanisms;reliability reports;software components;Bayes methods;Computational modeling;Estimation;Hardware;Software;Software reliability;cross-layer reliability;dependable computing system;reliability modeling
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