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Monday, 14 April 2014 15:11

Performance Assessment of Data Prefetchers in High Error Rate Technologies

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Foutris, N.; Gizopoulos, D.; Chatzidimitriou, A.;  Kalamatianos, J.; Sridharan, V., in Proceedings of the 10th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2014), Stanford, CA, USA, April 1-2, 2014



Modern microprocessors are equipped with an arsenal of speculative mechanisms, such as data prefetchers, to mitigate ever-growing memory access latency. Aggressive technology scaling along with near-threshold voltage operation exacerbates the likelihood and rate of hard faults not only in large arrays such as caches but in speculative components as well. While data prefetchers do not affect correct processor operation, they are critical for performance and faults in them can cause significant performance degradation and variability across otherwise identical cores. The impact of hard faults in data prefetchers has not been quantified accurately.
In this paper, we quantify the performance and variability impact of hard faults in stride data prefetchers. Our study reveals fault scenarios in the prefetcher table that can degrade IPC more than 17%, while faults in the prefetch input and request queues can slow IPC up to 24% and 26%, respectively, compared to a fault-free component. Finally, a faulty data prefetcher can increase performance variability across identical cores because the standard deviation of IPC loss for different benchmarks can be more than 4.5%.


  •  BIBTEX:
        author = {Foutris, N.and Gizopoulos, D. and Chatzidimitriou, A. and  Kalamatianos, J. and Sridharan, V.},
	title = {Performance Assessment of Data Prefetchers in High Error Rate Technologies},
	booktitle = {Proceedings of the 10th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2014)},
	year = {2014},
	month = {April},
  •  KEYWORDS: microprocessor, reliability, performance
Read 6607 times Last modified on Wednesday, 30 July 2014 14:49

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