Abstract
Modern SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly employed in safety- and mission-critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. Assessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing design exploration of different protection alternatives. This paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated infrastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.
Details
- BIBTEX:
@INPROCEEDINGS{6962073,
author={Di Carlo, S. and Prinetto, P. and Rolfo, D. and Trotta, P.},
booktitle={Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on},
title={A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs},
year={2014},
month={Oct},
pages={159-164},
doi={10.1109/DFT.2014.6962073},
}
- DOI: 10.1109/DFT.2014.6962073
- KEYWORDS: SRAM chips, field programmable gate arrays, integrated circuit design, radiation hardening (electronics)
