Abstract
Statistical Fault Injection on microarchitectural simulators can provide early and accurate reliability characterization for array based hardware components. Besides, microarchitectural fault injectors are easily configurable (facilitating many reliability studies) and orders of magnitude faster than RTL fault injectors, rendering them appropriate tools for early reliability estimation using large and realistic benchmarks. However, the throughput of the fault injection campaigns on microarchitectural simulators remains a bottleneck when a batch of campaigns must run for early reliability estimation of a processor (different microarchitectural characteristics, different workloads). This paper presents two different operation modes on top of a baseline framework for statistical fault injection campaigns, trading off between accuracy and speedup of the injection campaigns with a state-of-the-art out-of-order full-system x86-64 simulator as experimental vehicle. In the first mode, the injection experiments are stopped and classified as masked due to the following conditions: (i) the fault is over-written after the injection and it hasn’t been read earlier, (ii) or the fault is injected on an invalid entry. The second mode has the same termination conditions as the first mode, but the injection experiments can also be terminated when an instruction that has read the faulty entry passes through the commit stage of the x86-64 out-of-order architecture. In the first mode, we observed a speedup up to 2.92x with no loss of accuracy in the vulnerability measurements for all structures. In the second mode an even higher speedup of up to 4.06x has been obtained with small loss in the accuracy of the vulnerability measurements.
Details
- BIBTEX:
@INPROCEEDINGS{7315134,
author={M. Kaliorakis and S. Tselonis and A. Chatzidimitriou and D. Gizopoulos},
booktitle={Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on},
title={Accelerated microarchitectural Fault Injection-based reliability assessment},
year={2015},
pages={47-52},
keywords={fault diagnosis;performance evaluation;reliability;statistical analysis;RTL fault injector;accelerated microarchitectural fault injection;performance evolution;reliability assessment;reliability estimation;rendering;statistical fault injection;vulnerability measurement;x86-64 out-of-order architecture;Accuracy;Benchmark testing;Circuit faults;Estimation;Microarchitecture;Registers;Reliability;early reliability evaluation;microarchitectural simulators;microprocessors;statistical fault injection},
doi={10.1109/DFT.2015.7315134},
month={Oct},
}
- DOI: 10.1109/DFT.2015.7315134
- KEYWORDS: fault diagnosis;performance evaluation;reliability;statistical analysis;RTL fault injector;accelerated microarchitectural fault injection;performance evolution;reliability assessment;reliability estimation;rendering;statistical fault injection;vulnerability measurement;x86-64 out-of-order architecture;Accuracy;Benchmark testing;Circuit faults;Estimation;Microarchitecture;Registers;Reliability;early reliability evaluation;microarchitectural simulators;microprocessors;statistical fault injection
