Abstract
Advanced computing systems realized in forthcoming technologies hold the promise of a significant increase of computational capabilities. However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable. Developing new methods to evaluate the reliability of these systems in an early design stage has the potential to save costs, produce optimized designs and have a positive impact on the product time-to-market. CLERECO European FP7 research project addresses early reliability evaluation with a cross-layer approach across different computing disciplines, across computing system layers and across computing market segments. The fundamental objective of the project is to investigate in depth a methodology to assess system reliability early in the design cycle of the future systems of the emerging computing continuum. This paper presents a general overview of the CLERECO project focusing on the main tools and models that are being developed that could be of interest for the research community and engineering practice.
Details
- BIBTEX:
@article{Vallero20151204,
title = "Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A \{CLERECO\} \{EU\} project overview ",
journal = "Microprocessors and Microsystems ",
volume = "39",
number = "8",
pages = "1204 - 1214",
year = "2015",
note = "",
issn = "0141-9331",
author = "A. Vallero and S. Tselonis and N. Foutris and M. Kaliorakis and M. Kooli and A. Savino and G. Politano and A. Bosio and G. Di Natale and D. Gizopoulos and S. Di Carlo",
keywords = "Reliability evaluation",
keywords = "Fault injection",
keywords = "Statistical models "
}
- DOI: 10.1016/j.micpro.2015.06.003
- KEYWORDS: Reliability evaluation, Fault injection, Statistical models
