Abstract
With the advent of solid-state storage systems, NAND flash memories are becoming a key storage technology. However, they suffer from serious reliability and endurance issues during the operating lifetime that can be handled by the use of appropriate error correction codes (ECCs) in order to reconstruct the information when needed. Adaptable ECCs may provide the flexibility to avoid worst-case reliability design, thus leading to improved performance. However, a way to control such adaptable ECCs' strength is required. This article proposes FLARES, an algorithm able to adapt the ECC correction capability of each page of a flash based on a flash RBER prediction model and on a measurement of the number of errors detected in a given time window.
FLARES has been fully implemented within the YAFFS 2 filesystem under the Linux operating system. This allowed us to perform an extensive set of simulations on a set of standard benchmarks that highlighted the benefit of FLARES on the overall storage subsystem performances.
Details
- BIBTEX:
@ article{
Carlo:2014:FAA:2658949.2631919,
author={Di Carlo, Stefano and Galfano, Salvatore and Indaco, Marco and Prinetto, Paolo and Bertozzi, Davide and Olivo, Piero and Zambelli, Cristian},
title={FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories},
journal = {ACM Trans. Archit. Code Optim.},
year={2014},
month={July},
issue_date = {August 2014},
volume = {11},
number = {3},
month = jul,
year = {2014},
issn = {1544-3566},
pages = {26:1--26:25},
articleno = {26},
numpages = {25},
url = {https://doi.acm.org/10.1145/2631919},
doi = {10.1145/2631919},
acmid = {2631919},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {Adaptable ECC, BCH codes, NAND flash memory, error-correcting codes},
}
- DOI: 10.1145/2631919
- KEYWORDS:Adaptable ECC, BCH codes, NAND flash memory, error-correcting codes
