Abstract
Forthcoming technologies hold the promise of a significant increase in integration density, performance and functionality. However, a dramatic change in microprocessor's reliability is also expected. Developing mechanisms for early and accurate reliability estimation will save significant design effort, resources and consequently will positively impact product's time-to-market (TTM). In this paper, we propose a versatile architecture-level fault injection framework, built on top of a state-of-the-art x86 microprocessor simulator, for thorough and fast characterization of a wide range of hardware components with respect to various fault models.
Details
- BIBTEX:
@INPROCEEDINGS{
6873686,
author={Foutris, N. and Kaliorakis, M. and Tselonis, S. and Gizopoulos, D.},
booktitle={On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International},
title={Versatile architecture-level fault injection framework for reliability evaluation: A first report},
year={2014},
month={July},
pages={140-145}},
doi={10.1109/IOLTS.2014.6873686},
}
- DOI: 10.1109/IOLTS.2014.6873686
- KEYWORDS: fault diagnosis, integrated circuit reliability, microprocessor chips
